S3F84YB的特征详细信息
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S3F84YB芯片的特征介绍让更多的人链接 S3F84YB芯片的性能
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以下是S3F84YB的特征详细信息
Features
CPU
- SAM88 RC CPU core
Memory
- Program Memory (ROM)
- 64K × 8 bits program memory
- Internal flash memory (program memory)
- Sector size: 128 bytes
- 10 years data retention
- Fast programming time:
- User program and sector erase available
- Endurance: 10,000 erase/program cycles
- External serial programming support
- Expandable OBPTM (on board program) sector
- Data Memory (RAM)
- Including LCD display data memory
- 2,114 × 8 bits data memory
Instruction Set
- 78 instructions
- Idle and stop instructions added for power-down modes
70 I/O Pins
- I/O: 18 pins (Sharing with other signal pins)
- I/O: 52 pins (Sharing with LCD signal outputs)
Interrupts
- 8 interrupt levels and 31 interrupt sources
- Fast interrupt processing feature
8-Bit Basic Timer
- Watchdog timer function
- 4 kinds of clock source
8-Bit Timer/Counter A
- Programmable 8-bit internal timer
- External event counter function
- PWM and capture function
8-Bit Timer/Counter B
- Programmable 8-bit internal timer
- Carrier frequency generator
Two 16-Bit Timer/Counter (C0/C1)
- Programmable 8-bit internal timer
- PWM function
Two 16-Bit Timer/Counter (D0/D1)
- Programmable 16-bit internal timer
- External event counter function
- PWM and capture function
Watch Timer
- Interval time: 1.995mS, 0.125S, 0.25S, and 0.5S at 32.768 kHz
- 0.5/1/2/4 kHz Selectable buzzer output LCD Controller/Driver
- 44 segments and 8 common terminals
- 1/2, 1/3, 1/4, and 1/8 duty selectable
- Capacitor or resistor bias selectable
- Regulator and booster circuit for LCD bias
Analog to Digital Converter
- 8-channel analog input
- 10-bit conversion resolution
- 25uS conversion time
Digital to Analog Converter
- 1-channel analog output
- 8-bit conversion resolution (R-2R)
Two Channels UART
- Full-duplex serial I/O interface
- Four programmable operating modes
- Auto generating parity bit
8-bit Serial I/O Interface
- 8-bit transmit/receive mode
- 8-bit receive mode
- LSB-first or MSB-first transmission selectable
- Internal or external clock source
Pattern Generation Module
- Pattern generation module triggered by timer match signal and software
Low Voltage Reset (LVR)
- Criteria voltage: 2.2V
- En/Disable by smart option (ROM address: 3FH)
Two Power-Down Modes
- Idle: only CPU clock stops
- Stop: selected system clock and CPU clock stop
Oscillation Sources
- Crystal, ceramic, or RC for main clock
- Main clock frequency: 0.4 MHz ? 12.0 MHz
- 32.768 kHz crystal oscillation circuit for sub clock
Instruction Execution Times
- 333nS at 12.0 MHz fx (minimum)